VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Author(s): Abdul Kareem, Vardhana M., Praveen Kumar.

Journal Name: Recent Patents on Computer Science

Volume 9 , Issue 3 , 2016

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Background: Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed, area efficient and power efficient multiplier. Also, many patents emphasize on the fact that multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. Hence, there is a need for high speed- low power multipliers. This can be achieved by using the concept of Vedic Mathematics as multipliers based on Vedic Mathematics is one of the fast and low power multiplier Urdhva tiryakbhyam, Nikhilam, sutras forms the basic Vedic formulas in the design of Vedic multipliers.

Method: Existing systems for multiplication is studied and latest trends are studied and proposed system is developed. The design of high speed, low power, and area efficient multiplier using modified Vedic Mathematical technique. Vedic Mathematics is the ancient branch of Mathematics, which has a unique technique of calculations based on 16 Sutras. These sutras are time efficient and reduce the time and space. The complexity of the multiplication is reduced as the unwanted steps are eliminated. In this paper, Urdhva Tryagbhyam sutra is applied to the two bit multiplier and the formula is slightly modified and applied for the multiplication of higher order bits. A 16x16 multiplier is designed and simulated using Xilinx simulator. The timing report is compared with other techniques of multiplication, such as Karatsuba Array multiplier and also modified Radix-2 technique.

Results: The proposed IC for multiplier is designed and implemented in Cadence Encounter and proved the efficient use of Vedic Sutra. The comparison of the timing report reveals that the proposed multiplier consumes less time and is faster than the existing multipliers. The power details prove that the proposed multiplier consumes less power. The proposed design is implemented in VLSI using CADENCE tools and the IC design of the proposed multiplier is presented.

Conclusion: A modified Vedic mathematical technique based high speed, low power, area efficient multiplier is designed. The multiplier IC is designed in VLSI using cadence tool and the floor planning and power planning is done. The primitive cells are placed and are routed. The proposed multiplier is faster and consumes less area and power in comparison with the existing multipliers. Hence, the implementation of proposed multiplier using modified Vedic mathematics has proved the efficient use of Vedic sutras and proved to be the efficient in comparison with the existing multipliers.

Keywords: Vedic sutra, karatsuba algorithm, DFT, array multiplier, radix-4 technique, urdhva tryagbhyam sutra.

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Article Details

Year: 2016
Page: [216 - 221]
Pages: 6
DOI: 10.2174/2213275908666150220203501
Price: $58

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