Designs and Implementations of Energy-Efficient Single-Phase Clock Pass Transistor Adiabatic Logic Circuits
In current nanometer circuits, energy consumptions of the high-performance chips have become a critical concern.
Adiabatic computing reduces energy dissipations by using AC power supplies to recycle the energy stored in node
capacitances of the circuits. Adiabatic logic circuits only using a single-phase power clock do not need multiple powerclock
generators and complicated clock trees, and thus are easily implemented. In this paper, recent patents and progress
on adiabatic computing are reviewed. The structure and operation of a single-phase adiabatic logic named as SCPTAL
(single-phase clock pass transistor adiabatic logic) are presented in detail. The design methods of the logic cells based on
SCPTAL, such as basic gates, full adder, 5-2 compressor, and flip-flops, are also addressed. The energy comparisons between
the SCPTAL and static CMOS cells are carried out. The results show that the SCPTAL circuits have large energy
savings over a wide range of frequencies, as compared with conventional static CMOS logic ones, which can be a good
candidate for ultra-low power applications.
Keywords: Adiabatic computing, digital circuits, energy recovery, low power design, nanometer circuits, single-phase
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