In this paper we have implemented the semi-empirical compact model for CNTFETs already proposed by us both in SPICE,
using ABM library, and in Verilog-A in order to compare them.
Typical analogue circuits and logic blocks have been simulated and results have been presented to validate the implementation of the proposed
CNTFET model both in Verilog-A and in SPICE.
The obtained results have been the same in static simulations and comparable in dynamic simulations, in which the differences are due to
the better implementation of the capacitance model in Verilog-A.
We have found many advantages using Verilog-A: the development time in writing the model is shorter, the simulation run time much
shorter and the software is much more concise and clear than schemes using ABM blocks in SPICE.